(Intel 1.2 ver Base) Datasheet
128M X 72 SDRAM DIMM With PLL & Register Based On Stacked 128Mx4, 4Banks 8K Ref.,
Download: (Intel 1.2 ver Base) Datasheet 
(Intel 1.2 ver Base)
128M X 72 SDRAM DIMM With PLL & Register Based On Stacked 128Mx4, 4Banks 8K Ref.,
M377S2858CT3
PC100 Registered DIMM
M377S2858CT3 SDRAM DIMM (Intel 1.2 ver Base)
128mx72 Sdram Dimm With Pll & Register Based On Stacked 128mx4, 4banks 8k Ref., 3.3v Sdrams With Spd
GENERAL
Description
The Samsung M377s2858ct3 Is A 128m Bit X 72 Synchronous Dynamic Ram High Density Memory Module. The
Samsung M377s2858ct3 Consists Of Eighteen Cmos Stacked 128mx4 Bit Synchronous Drams In Two Tsop-ii
400mil Packages, Three 18-bits Drive Ics For Input Control Signal, One Pll In 24-pin Tssop Package
For Clock And One 2k Eeprom In 8pin Tssop Package For Serial Presence Detect On A 168-pin
Glass-epoxy Substrate. Two 0.22uf And One 0.0022uf Decoupling Capacitors Are Mounted On The Printed
Circuit Board In Parallel For Each Sdram. The M377s2858ct3 Is A Dual Inline Memory Module And Is
Intented For Mounting Into 168-pin Edge Connector Sockets. Synchronous Design Allows Precise Cycle
Control With The Use Of System Clock. I/o Transactions Are Possible On Every Clock Cycle. Range Of
Operating Frequencies, Programmable Latencies Allows The Same Device To Be Useful For A Variety Of
high bandwidth, high performance memory system
Applications.
FEATURE
Performance range
Part No. M377S2858CT3-C1H M377S2858CT3-C1L
Max Freq. (Speed) 100MHz (10ns @ CL=2) 100MHz (10ns @ CL=3)
Burst mode operation
Auto & self refresh capability (8192 Cycles/64ms)
LVTTL compatible inputs and outputs
Single 3.3V 0.3V power supply
MRS cycle with address key programs
Latency (access From Column Address) Burst Length (1, 2, 4 , 8 & Full Page) Data Scramble
(Sequential & Interleave)
All inputs are sampled at the positive going edge of the system clock
Serial presence detect with EEPROM
PCB : Height (1,700mil), double sided component
PIN CONFIGURATIONS (Front side/back side)
PIN NAMES
Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back
Pin Name
Function
1 Vss 29 Dqm1 57 Dq18 85 Vss 113 Dqm5 141 Dq50 2 Dq0 30 Cs0 58 Dq19 86 Dq32 114 Cs1 142 Dq51
A0 ~ A12 BA0 ~ BA1
Address input (Multiplexed) Select bank
(Intel 1.2 ver Base) Datasheet
128M X 72 SDRAM DIMM With PLL & Register Based On Stacked 128Mx4, 4Banks 8K Ref.,
Download: (Intel 1.2 ver Base) Datasheet
(Intel 1.2 ver Base)
128M X 72 SDRAM DIMM With PLL & Register Based On Stacked 128Mx4, 4Banks 8K Ref.,
M377S2858BT3
PC100 Registered DIMM
M377S2858BT3 SDRAM DIMM (Intel 1.2 ver Base)
128mx72 Sdram Dimm With Pll & Register Based On Stacked 128mx4, 4banks 8k Ref., 3.3v Sdrams With Spd
GENERAL
Description
The Samsung M377s2858bt3 Is A 128m Bit X 72 Synchronous Dynamic Ram High Density Memory Module. The
Samsung M377s2858bt3 Consists Of Eighteen Cmos Stacked 128mx4 Bit Synchronous Drams In Two Tsop-ii
400mil Packages, Three 18-bits Drive Ics For Input Control Signal, One Pll In 24-pin Tssop Package
For Clock And One 2k Eeprom In 8pin Tssop Package For Serial Presence Detect On A 168-pin
Glass-epoxy Substrate. Two 0.22uf And One 0.0022uf Decoupling Capacitors Are Mounted On The Printed
Circuit Board In Parallel For Each Sdram. The M377s2858bt3 Is A Dual In-line Memory Module And Is
Intented For Mounting Into 168-pin Edge Connector Sockets. Synchronous Design Allows Precise Cycle
Control With The Use Of System Clock. I/o Transactions Are Possible On Every Clock Cycle. Range Of
Operating Frequencies, Programmable Latencies Allows The Same Device To Be Useful For A Variety Of
high bandwidth, high performance memory system
Applications.
FEATURE
Performance range
Part No. M377S2858BT3-C1H M377S2858BT3-C1L
Max Freq. (Speed) 100MHz (10ns @ CL=2) 100MHz (10ns @ CL=3)
Burst mode operation
Auto & self refresh capability (8192 Cycles/64ms)
LVTTL compatible inputs and outputs
Single 3.3V 0.3V power supply
MRS cycle with address key programs
Latency (access From Column Address) Burst Length (1, 2, 4 , 8 & Full Page) Data Scramble
(Sequential & Interleave)
All inputs are sampled at the positive going edge of the system clock
Serial presence detect with EEPROM
PCB : Height (1,700mil), double sided component
PIN CONFIGURATIONS (Front side/back side)
PIN NAMES
Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back
Pin Name
Function
1 Vss 29 Dqm1 57 Dq18 85 Vss 113 Dqm5 141 Dq50 2 Dq0 30 Cs0 58 Dq19 86 Dq32 114 Cs1 142 Dq51
A0 ~ A12 BA0 ~ BA1
Address input (Multiplexed) Select bank