ATSAMA5D28B-CUR Datasheet
Integrated Circuits (ICs) - Embedded - Microprocessors - IC MCU 32BIT 289LFBGA
Download: ATSAMA5D28B-CUR Datasheet 
ATSAMA5D28B-CUR
Integrated Circuits (ICs) - Embedded - Microprocessors - IC MCU 32BIT 289LFBGA
32-BIT ARM-BASED MICROPROCESSORS
SAMA5D2 Series SAMA5D21 /22 /23 /24 /26 /27 /28
Introduction
The Sama5d2 Series Is A High-performance, Ultra-low-power Arm Cortex -a5 Processor-based Mpu Running
Up To 500 Mhz, With Support For Multiple Memories Such As Ddr2, Ddr3, Ddr3l, Lpddr1, Lpddr2, Lpddr3,
And Qspi Flash. The Devices Integrate Powerful Peripherals For Connectivity And User Interface
Applications, And Offer Advanced Security Functions (arm Trustzone , Tamper Detection, Secure Data
storage, etc.), as well as high-performance cryptoprocessors AES, SHA and TRNG.
The Sama5d2 Series Is Delivered With A Free Linux Distribution And Bare Metal C Examples.
FEATURES
Arm Cortex-a5 Core - Armv7-a Architecture - Arm Trustzone - Neon Media Processing Engine - Up To 500
MHz - ETM/ETB 8 Kbytes
Memory Architecture - Memory Management Unit - 32-kbyte L1 Data Cache, 32-kbyte L1 Instruction Cache
- 128-kbyte L2 Cache Configurable To Be Used As An Internal Sram - One 128-kbyte Scrambled Internal
Sram - One 160-kbyte Internal Rom 64-kbyte Scrambled And Maskable Rom Embedding Boot Loader/
Secure Boot Loader 96-kbyte Unscrambled, Unmaskable Rom For Nand Flash Bch Ecc Table -
High-bandwidth Scramblable 16-bit Or 32-bit Double Data Rate (ddr) Multiport Dynamic Ram Controller
Supporting Up To 512 Mbyte 8-bank Ddr2/ddr3 (dll Off Only) / Ddr3l (dll Off Only) / Lpddr1/lpddr2/
Lpddr3, Including "on-the-fly" Encryption/decryption Path - 8-bit Slc/mlc Nand Controller, With Up
to 32-bit Error Correcting Code (PMECC)
System Running Up To 166 Mhz In Typical Conditions - Reset Controller, Shutdown Controller, Periodic
Interval Timer, Independent Watchdog Timer And Secure Real-time Clock (rtc) With Clock Calibration -
One 600 To 1200 Mhz Pll For The System And One 480 Mhz Pll Optimized For Usb High Speed - Digital
Fractional Pll For Audio (11.2896 Mhz And 12.288 Mhz) - Internal Low-power 12 Mhz Rc And 32 Khz
Typical Rc - Selectable 32.768-hz Low-power Oscillator And 8 To 24 Mhz Oscillator - 51 Dma Channels
Including Two 16-channel 64-bit Central Dma Controllers - 64-bit Advanced Interrupt Controller (aic)
- 64-bit Secure Advanced Interrupt Controller (saic) - Three Programmable External Clock Signals
Low-power Modes - Ultra Low-power Mode With Fast Wakeup Capability - Low-power Backup Mode With
5-Kbyte SRAM and SleepWalking
Features Wakeup From Up To Nine Wakeup Pins, Uart Reception, Analog Comparison Fast Wakeup
capability
2017 Microchip Technology
DS60001476B-page 1
SAMA5D2 SERIES
Extended Backup mode with DDR in Self-Refresh mode
Peripherals - Lcd Tft Controller Up To 1024x768, With Four Overlays, Rotation, Post-processing And
Alpha Blending, 24-bit Parallel Rgb - Itu-r Bt. 601/656/1120 Image Sensor Controller (isc)
Supporting Up To 5 M-pixel Sensors With A Parallel 12-bit Interface For Raw Bayer, Ycbcr, Monochrome
And Jpeg-compressed Sensor Interface - Two Synchronous Serial Controllers (ssc), Two Inter-ic Sound
Controllers (i2sc), And One Stereo Class D Amplifier - One Peripheral Touch Controller (ptc) With Up
To 8 X-lines And 8 Y-lines (64-channel Capacitive Touch) - One Pulse Density Modulation Interface
Controller (pdmic) - One Usb High-speed Device Port (udphs) And One Usb High-speed Host Port Or Two
Usb High-speed Host Ports (uhphs) - One Usb High-speed Host Port With A High-speed Inter-chip (hsic)
Interface - One 10/100 Ethernet Mac (gmac) Energy Efficiency Support (ieee 802.3az Standard)
Ethernet Avb Support With Ieee802.1as Time Stamping Ieee802.1qav Credit-based Traffic-shaping
hardware support IEEE1588 Precision Time Protocol (PTP)
- Two High-speed Memory Card Hosts: Sdmmc0: Sd 3.0, Emmc 4.51, 8 Bits Sdmmc1: Sd 2.0, Emmc
4.41, 4 bits only
- Two Master/slave Serial Peripheral Interfaces (spi) - Two Quad Serial Peripheral Interfaces (qspi)
- Five Flexcoms (usart, Spi And Twi) - Five Uarts - Two Master Can-fd (mcan) Controllers With
Sram-based Mailboxes, And Time- And Event-triggered Transmission - One Rx Only Uart In Backup Area
(rxlp) - One Analog Comparator (acc) In Backup Area - Two 2-wire Interfaces (twihs) Up To 400
Kbits/s Supporting The I2c Protocol And Smbus (twihs) - Two 3-channel 32-bit Timer/counters (tc),
Supporting Basic Pwm Modes - One Full-featured 4-channel 16-bit Pulse Width Modulation (pwm)
Controller - One 12-channel, 12-bit, Analog-to-digital Converter (adc) With Resistive Touchscreen
capability
Safety - Zero-power-on Reset (por) Cells - Main Crystal Clock Failure Detector - Write-protected
Registers - Integrity Check Monitor (icm) Based On Sha256 - Memory Management Unit - Independent
watchdog
Security - 5 Kbytes of internal scrambled SRAM:
1 Kbyte Non-erasable On Tamper Detection 4 Kbytes Erasable On Tamper Detection
- 256 Bits Of Scrambled And Erasable Registers - Up To Eight Tamper Pins For Static Or Dynamic
Intrusion Detections - Environmental Monitors On Specific Versions: Temperature, Voltage, Frequency
And Active Die Shield(1) - Secure Boot Loader(2) - On-the-fly Aes Encryption/decryption On Ddr And
Qspi Memories (aesb) - Rtc Including Time-stamping On Security Intrusions - Programmable Fuse Box
With 544 Fuse Bits (including Jtag Protection And Bms) Note 1: For Environmental Monitors, Refer To
the document "SAMA5D23 and SAMA5D28 Environmental Monitors" (document
No. 44036), Available Under Non-disclosure Agreement (nda). Contact A Microchip Sales Representative
for details.
2: For Secure Boot Strategies, Refer To The Document "sama5d2 Series Secure Boot Strategy" (document
No. 44040), Available Under Non-disclosure Agreement (nda). Contact A Microchip Sales Representative
for details.
Hardware Cryptography - Sha (sha1, Sha224, Sha256, Sha384, Sha512): Compliant With Fips Pub 180-2 -
AES: 256-, 192-, 128-bit key algorithm, compliant with FIPS PUB 197
DS60001476B-page 2
2017 Microchip Technology
SAMA5D2 SERIES
- Tdes: Two-key Or Three-key Algorithms, Compliant With Fips Pub 46-3 - True Random Number Generator
(trng) Compliant With Nist Special Publication 800-22 Test Suite And Fips Pubs 140-2 And