CD4007 Datasheet
Dual Complementary Pair Plus Inverter
Download: CD4007 Datasheet 
CD4007
Dual Complementary Pair Plus Inverter
CD4007C Dual Complementary Pair Plus Inverter
October 1987 Revised January 1999
CD4007C Dual Complementary Pair Plus Inverter
General
Description
The Cd4007c Consists Of Three Complementary Pairs Of Nand P-channel Enhancement Mode Mos Transistors
suitable for series/shunt
Applications. All Inputs Are Protected From Static Discharge By Diode Clamps To Vdd And Vss.
For Proper Operation The Voltages At All Pins Must Be Constrained To Be Between Vss 0.3v And Vdd
+ 0.3V at all times.
FEATURES
Wide supply voltage range: 3.0V to 15V s High noise immunity: 0.45 VCC (typ.)
Ordering Code:
Order Number Package Number
Package
Description
CD4007CM
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow
CD4007CN
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices Also Available In Tape And Reel. Specify By Appending The Suffix Letter "x" To The Ordering
code.
Connection Diagram
Pin Assignments for DIP and SOIC
Note: All P-channel Substrates Are Connected To Vdd And All N-channel Substrates Are Connected To
VSS.
Top View
1999 Fairchild Semiconductor Corporation DS005943.prf
CD4007C
CD4007 Datasheet
CMOS Dual Complementary Pair Plus Inverter
Download: CD4007 Datasheet
CD4007
CMOS Dual Complementary Pair Plus Inverter
CD4007UBMS
November 1994
FEATURES
Pinout
High-Voltage Type (20V Rating)
Standardized Symmetrical Output Characteristics
Medium Speed Operation
- tPHL, tPLH = 30 ns (typ) at 10V
100% Tested for Maximum Quiescent Current at 20V
Meets All Requirements of JEDEC Tentative Stan-
dards No. 13B, "Standard Speci cations for
Description of "B" Series CMOS Devices"
Maximum Input Current Of 1 A At 18v Over Full Package-temperature Range; 100na At 18v And +25oc
Applications
Q2 (P) DRAIN 1
Q2 (P) SOURCE 2
Q2 GATES 3
Q2 (N) SOURCE 4
Q2 (N) DRAIN 5
Q1 GATES 6
VSS, Q1, Q2, Q3 (N) 7 SUBSTRATES Q1 (N) SOURCE
CD4007UBMS TOP VIEW
14 VDD, Q1, Q2, Q3 (P) SUBSTRATES, Q1(P) DRAIN
13 Q1 (p) Source 12 Q3 (n) Drain, Q3 (p) Source 11 Q3 (p) Drain 10 Q3 Gates 9 Q3 (n) Source 8 Q1 (n)
DRAIN
Extremely High-Input Impedance Ampli ers
Shapers
Inverters
Threshold Detector
Linear Ampli ers
Crystal Oscillators
Description
CD4007 Datasheet
Dual Complementary Pair Plus Inverter
Download: CD4007 Datasheet
CD4007
Dual Complementary Pair Plus Inverter
CD4007M CD4007C Dual Complementary Pair Plus Inverter
General
Description
The Cd4007m Cd4007c Consists Of Three Complementary Pairs Of N- And P-channel Enhancement Mode Mos
transistors suitable for series shunt
Applications All Inputs Are Protected From Static Discharge By Diode Clamps To Vdd And Vss
For Proper Operation The Voltages At All Pins Must Be Constrained To Be Between Vss B 0 3v And Vdd A
0 3V at all times
FEATURES
Y Wide supply voltage range Y High noise immunity
Connection Diagram
Dual-In-Line Package
February 1988
3 0V to 15V 0 45 VCC (typ )
Top View
Note All P-channel Substrates Are Connected To Vdd And All N-channel Substrates Are Connected To Vss
Order Number CD4007
TL F 5943 - 1
C1995 National Semiconductor Corporation TL F 5943
RRD-B30M105 Printed in
Absolute
MAXIMUM RATINGS (Note 1)
If Military Aerospace Specified Devices Are Required Please Contact The National Semiconductor Sales
Office Distributors for availability and specifications
Voltage at Any Pin
Operating Temperature Range CD4007M CD4007C
VSS b0 3V to VDD a0 3V
b55 C to a125 C b40 C to a85 C
Storage Temperature Range
Power Dissipation (PD) Dual-In-Line Small Outline
Operating VDD Range Lead Temperature
(Soldering 10 seconds)
b65 C to a150 C