DS90C383MTD Datasheet
+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz,
Download: DS90C383MTD Datasheet 
DS90C383MTD
+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz,
Ds90c383/ds90cf384 +3.3v Programmable Lvds 24-bit-color Flat Panel Display (fpd) Link - 65 Mhz
September 1999
Ds90c383/ds90cf384 +3.3v Programmable Lvds Transmitter 24-bit Flat Panel Display (fpd) Link- 65 Mhz,
+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link- 65 MHz
General
Description
The Ds90c383 Transmitter Converts 28 Bits Of Cmos/ttl Data Into Four Lvds (low Voltage Differential
Signaling) Data Streams. A Phase-locked Transmit Clock Is Transmitted In Parallel With The Data
Streams Over A Fifth Lvds Link. Every Cycle Of The Transmit Clock 28 Bits Of Input Data Are Sampled
And Transmitted. The Ds90cf384 Receiver Converts The Lvds Data Streams Back Into 28 Bits Of Cmos/ttl
Data. At A Transmit Clock Frequency Of 65 Mhz, 24 Bits Of Rgb Data And 3 Bits Of Lcd Timing And
Control Data (fpline, Fpframe, Drdy) Are Transmitted At A Rate Of 455 Mbps Per Lvds Data Channel.
Using A 65 Mhz Clock, The Data Throughputs Is 227 Mbytes/sec. The Transmitter Is Offered With
Programmable Edge Data Strobes For Convenient Interface With A Variety Of Graphics Controllers. The
Transmitter Can Be Programmed For Rising Edge Strobe Or Falling Edge Strobe Through A Dedicated Pin.
A Rising Edge Transmitter Will Inter-operate With A Falling Edge Receiver (ds90cf384) Without Any
Translation Logic. The Ds90cf384 Is Also Offered In 64 Ball, 0.8mm Fine Pitch Ball Grid Array(fbga)
package which provides a 44 % reduction in PCB footprint (available Q3, 1999).
This Chipset Is An Ideal Means To Solve Emi And Cable Size Problems Associated With Wide, High Speed
TTL interfaces.
FEATURES
N 20 To 65 Mhz Shift Clock Support N Programmable Transmitter (ds90c383) Strobe Select
(Rising or Falling edge strobe) n Single 3.3V supply
N Chipset (tx + Rx) Power Consumption < 250 Mw (typ) N Power-down Mode (< 0.5 Mw Total)
N Single Pixel Per Clock Xga (1024x768) Ready N Supports Vga, Svga, Xga And Higher Addressability. N
Up To 227 Megabytes/sec Bandwidth N Up To 1.8 Gbps Throughput N Narrow Bus Reduces Cable Size And
Cost N 290 Mv Swing Lvds Devices For Low Emi N Pll Requires No External Components N Low Profile
56-lead TSSOP package. n DS90CF384 also available in 64 ball, 0.8mm fine pitch
Ball Grid Array(fbga) Package N Falling Edge Data Strobe Receiver N Compatible With Tia/eia-644 Lvds
standard
n ESD rating >7 kV
n Operating Temperature: 40 C to +85 C
Block Diagrams
Application
DS012887-2
TRI-STATE is a registered trademark of National Semiconductor Corporation.
1999 National Semiconductor Corporation DS012887
Block Diagrams (Continued)
DS90C383
Order Number DS90C383MTD See NS Package Number MTD56
DS90CF384
DS012887-1
DS012887-24
Order Number DS90CF384MTD or DS90CF384SLC See NS Package Number MTD56 or SLC64A
Absolute
MAXIMUM RATINGS (Note 1)
If Military/aerospace Specified Devices Are Required, Please Contact The National Semiconductor
Sales Office/ Distributors for availability and specifications.
DS90C383MTD Datasheet
DS90C383/DS90CF384 +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display
Download: DS90C383MTD Datasheet
DS90C383MTD
DS90C383/DS90CF384 +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display
Ds90c383/ds90cf384 +3.3v Programmable Lvds 24-bit-color Flat Panel Display (fpd) Link-65 Mhz
November 2000
Ds90c383/ds90cf384 +3.3v Programmable Lvds Transmitter 24-bit Flat Panel Display (fpd) Link-65 Mhz,
+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz
General
Description
The Ds90c383 Transmitter Converts 28 Bits Of Lvcmos/ Lvttl Data Into Four Lvds (low Voltage
Differential Signaling) Data Streams. A Phase-locked Transmit Clock Is Transmitted In Parallel With
The Data Streams Over A Fifth Lvds Link. Every Cycle Of The Transmit Clock 28 Bits Of Input Data Are
Sampled And Transmitted. The Ds90cf384 Receiver Converts The Lvds Data Streams Back Into 28 Bits Of
Lvcmos/ Lvttl Data. At A Transmit Clock Frequency Of 65 Mhz, 24 Bits Of Rgb Data And 3 Bits Of Lcd
Timing And Control Data (fpline, Fpframe, Drdy) Are Transmitted At A Rate Of 455 Mbps Per Lvds Data
Channel. Using A 65 Mhz Clock, The Data Throughputs Is 227 Mbytes/sec. The Transmitter Is Offered
With Programmable Edge Data Strobes For Convenient Interface With A Variety Of Graphics Controllers.
The Transmitter Can Be Programmed For Rising Edge Strobe Or Falling Edge Strobe Through A Dedicated
Pin. A Rising Edge Transmitter Will Inter-operate With A Falling Edge Receiver (ds90cf384) Without
Any Translation Logic. Both Devices Are Also Offered In A 64 Ball, 0.8mm Fine Pitch Ball Grid Array
(fbga) Package Which Provides A 44 % Reduction In Pcb Footprint Compared To The Tssop Package.
This Chipset Is An Ideal Means To Solve Emi And Cable Size Problems Associated With Wide, High Speed
TTL interfaces.
FEATURES
N 20 To 65 Mhz Shift Clock Support N Programmable Transmitter (ds90c383) Strobe Select
(Rising or Falling edge strobe) n Single 3.3V supply
N Chipset (tx + Rx) Power Consumption < 250 Mw (typ) N Power-down Mode (< 0.5 Mw Total)
N Single Pixel Per Clock Xga (1024x768) Ready N Supports Vga, Svga, Xga And Higher Addressability. N
Up To 227 Megabytes/sec Bandwidth N Up To 1.8 Gbps Throughput N Narrow Bus Reduces Cable Size And
Cost N 290 Mv Swing Lvds Devices For Low Emi N Pll Requires No External Components N Low Profile
56-lead TSSOP package. n Also available in a 64 ball, 0.8mm fine pitch ball grid
Array (fbga) Package N Falling Edge Data Strobe Receiver N Compatible With Tia/eia-644 Lvds Standard
n ESD rating >7 kV
n Operating Temperature: 40 C to +85 C
Block Diagrams
Typical
Application
DS012887-2
TRI-STATE is a registered trademark of National Semiconductor Corporation.
2000 National Semiconductor Corporation DS012887
DS90C383/DS90CF384
Block Diagrams (Continued)
DS90C383
Order Number DS90C383MTD or DS90C383SLC See NS Package Number MTD56 or SLC64A
DS90CF384
DS012887-1
DS012887-24
Order Number DS90CF384MTD or DS90CF384SLC See NS Package Number MTD56 or SLC64A
DS90C383/DS90CF384
DS90C383MTD Datasheet
DS90CF383 - +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD)
Download: DS90C383MTD Datasheet
DS90C383MTD
DS90CF383 - +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD)
DS90C383
Ds90c383/ds90cf384 +3.3v Programmable Lvds Transmitter 24-bit Flat Panel Display (fpd) Link-65 Mhz,
+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz
Literature Number: SNLS124A
Ds90c383/ds90cf384 +3.3v Programmable Lvds 24-bit-color Flat Panel Display (fpd) Link-65 Mhz
November 2000
Ds90c383/ds90cf384 +3.3v Programmable Lvds Transmitter 24-bit Flat Panel Display (fpd) Link-65 Mhz,
+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz
General
Description
The Ds90c383 Transmitter Converts 28 Bits Of Lvcmos/ Lvttl Data Into Four Lvds (low Voltage
Differential Signaling) Data Streams. A Phase-locked Transmit Clock Is Transmitted In Parallel With
The Data Streams Over A Fifth Lvds Link. Every Cycle Of The Transmit Clock 28 Bits Of Input Data Are
Sampled And Transmitted. The Ds90cf384 Receiver Converts The Lvds Data Streams Back Into 28 Bits Of
Lvcmos/ Lvttl Data. At A Transmit Clock Frequency Of 65 Mhz, 24 Bits Of Rgb Data And 3 Bits Of Lcd
Timing And Control Data (fpline, Fpframe, Drdy) Are Transmitted At A Rate Of 455 Mbps Per Lvds Data
Channel. Using A 65 Mhz Clock, The Data Throughputs Is 227 Mbytes/sec. The Transmitter Is Offered
With Programmable Edge Data Strobes For Convenient Interface With A Variety Of Graphics Controllers.
The Transmitter Can Be Programmed For Rising Edge Strobe Or Falling Edge Strobe Through A Dedicated
Pin. A Rising Edge Transmitter Will Inter-operate With A Falling Edge Receiver (ds90cf384) Without
Any Translation Logic. Both Devices Are Also Offered In A 64 Ball, 0.8mm Fine Pitch Ball Grid Array
(fbga) Package Which Provides A 44 % Reduction In Pcb Footprint Compared To The Tssop Package.
This Chipset Is An Ideal Means To Solve Emi And Cable Size Problems Associated With Wide, High Speed
TTL interfaces.
FEATURES
N 20 To 65 Mhz Shift Clock Support N Programmable Transmitter (ds90c383) Strobe Select
(Rising or Falling edge strobe) n Single 3.3V supply
N Chipset (tx + Rx) Power Consumption < 250 Mw (typ) N Power-down Mode (< 0.5 Mw Total)
N Single Pixel Per Clock Xga (1024x768) Ready N Supports Vga, Svga, Xga And Higher Addressability. N
Up To 227 Megabytes/sec Bandwidth N Up To 1.8 Gbps Throughput N Narrow Bus Reduces Cable Size And
Cost N 290 Mv Swing Lvds Devices For Low Emi N Pll Requires No External Components N Low Profile
56-lead TSSOP package. n Also available in a 64 ball, 0.8mm fine pitch ball grid
Array (fbga) Package N Falling Edge Data Strobe Receiver N Compatible With Tia/eia-644 Lvds Standard
n ESD rating >7 kV
n Operating Temperature: 40 C to +85 C
Block Diagrams
Typical
Application
DS012887-2
TRI-STATE is a registered trademark of National Semiconductor Corporation.
2000 National Semiconductor Corporation DS012887
DS90C383/DS90CF384
Block Diagrams (Continued)
DS90C383
Order Number DS90C383MTD or DS90C383SLC See NS Package Number MTD56 or SLC64A
DS90CF384
DS012887-1