MC9S12NE64 Datasheet
16-bit Microcontroller
Download: MC9S12NE64 Datasheet 
MC9S12NE64
16-bit Microcontroller
MC9S12NE64
Target
Applications
> Industrial Controls
> Automotive Meter
> Network Appliances
Reading
> Remote Equipment
> Vending Machines
> Ethernet-Enabled Games > Home/Office Automation
> Ethernet Bridge
The Hcs12 Family Of Microcontrollers Is The Next Generation Of The Highly Successful 68hc12
Architecture. Using Freescale Semiconductor's 0.25 Flash, The Mc9s12ne64 Provides An Upward
migration path from the 68HC08, 68HC11 and 68HC12 architectures for
Applications that need larger memory, more peripherals and higher performance.
The Mc9s12ne64 Provides A Total Ethernet Connectivity Solution In One Microcontroller Unit (mcu)
With Its Integrated Ethernet Media Access Controller (emac), 10/100 Ethernet Physical Layer (ephy)
and on-chip Flash memory.
Features Include Two Serial Communications Interfaces (scis), A Four-channel Timer, A Serial
Peripheral Interface (spi), An Inter-integrated Circuit (i2c) And A 10-bit Analog To Digital
converter (ADC).
BLOCK DIAGRAM HCS12 CPU with Debug Module
2 x SCI
64K Flash
Voltage Regulator 3.3 V to 2.5 V Converter
18-Key Wake-up IRQ Ports
ADC 10-bit, 8-ch.
Timer 16-bit, 4-ch.
Internal Bus
8K RAM EPHY EMAC
FEATURES High-Performance 16-bit HCS12 CPU Core
> 25 MHz operation at 3.3 V for 40 nsec minimum instruction cycle time
MC9S12NE64 Datasheet
Microcontrollers
Download: MC9S12NE64 Datasheet
MC9S12NE64
Microcontrollers
MC9S12NE64
Data Sheet
HCS12 Microcontrollers
MC9S12NE64V1 Rev. 1.1 06/2006
MC9S12NE64 Data Sheet
MC9S12NE64V1 Rev. 1.1 06/2006
To Provide The Most Up-to-date Information, The Revision Of Our Documents On The World Wide Web Will
Be The Most Current. Your Printed Copy May Be An Earlier Revision. To Verify You Have The Latest
information available, refer to:
The Following Revision History Table Summarizes Changes Contained In This Document.
Revision History
Date September, 2004
June 27, 2006
Revision Level 1.0
Description
Initial External Release. Fixed Labels For Addresses $0167-$0169 On Detailed Register Map. Updated
PHY Rx and Tx ESD protection characteristics on Table A-3.
Freescale And The Freescale Logo Are Trademarks Of Freescale Semiconductor This Product Incorporates
Superflash Technology Licensed From Sst. Freescale Semiconductor, 2006. All Rights Reserved.
MC9S12NE64 Data Sheet, Rev. 1.1 4
Freescale Semiconductor
LIST OF CHAPTERS
Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9 Chapter 10
Chapter 11 Chapter 12 Chapter 13 Chapter 14 Chapter 15 Chapter 16 Chapter 17 Chapter 18
Mc9s12ne64 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . 19 64 Kbyte Flash
Module (s12fts64kv3) . . . . . . . . . . . . . . . . . . 67 Port Integration Module (pim9ne64v1) . .
. . . . . . . . . . . . . . . 105 Clocks And Reset Generator (crgv4) . . . . . . . . . . . . . . . .
. . 141 Oscillator (oscv2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Timer Module (tim16b4cv1) . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Analog-to-digital
Converter (atd10b8cv3) . . . . . . . . . . . . . 205 Serial Communication Interface (sciv3) . . . .
. . . . . . . . . . . . 229 Serial Peripheral Interface (spiv3) . . . . . . . . . . . . . . . . . .
. . . 261 Inter-integrated Circuit (iicv2) . . . . . . . . . . . . . . . . . . . . . . . . 283
Ethernet Media Access Controller (emacv1) . . . . . . . . . . . . 307 Ethernet Physical Transceiver
(ephyv2). . . . . . . . . . . . . . . . 347 Penta Output Voltage Regulator (vregphyv1) . . . . . . .
. . . 379 Interrupt (intv1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
387 Multiplexed External Bus Interface (mebiv3) . . . . . . . . . . . . 395 Module Mapping Control
(mmcv4) . . . . . . . . . . . . . . . . . . . . . 423 Background Debug Module (bdmv4). . . . . . . .
. . . . . . . . . . . 443 Debug Module (dbgv1) . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 469
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
Chapter 1 MC9S12NE64 Device Overview
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . 19 1.1.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 19 1.1.2 Modes Of Operation . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.1.3 Block Diagram . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. 22 1.1.4 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 23 1.1.5 Detailed Register Map . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.1.6 Part Id Assignments . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
1.2 Signal
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . 40 1.2.1 Device Pinout . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 1.2.2 Signal Properties
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. 43 1.2.3 Detailed Signal